13 Jan 2004


Started to work seriously at the “Electronics of Digital Systems” assignment (design and implement on a test FPGA board an UART in Verilog). Until yesterday I didn’t do much more than find out what a UART is.
We split the thing in 4 parts:

  • Transmitter
  • Receiver
  • BaudClock Generator
  • Bus Control

I think I have pretty clear idea of how to implement each component, but I didn’t imagine that was such a pain passing from the “alogorithm” (eg “oh ok, the txmit is a state machine that does this and that”) to a working (where working means “it passes all the test benches”) module.
Extra grief was caused by the crappy Xilinx tools.
We started from the BaudClock Generator: it’s a relly simple component that given the system clock and the selected baudrate outputs a clock which is 16x the baudrate; for example, this clock is used in the receiver to do triple sampling on the incoming bits.
Basically it’s nothing more than counting up to N and switch, counting up to N and switch, etc.
It passes the behavioural simulation just fine, but when we mapped it, all we got as output is wire connected to ground. Wonderful.


Yesterday paolo committed a big patch, which among other things introduces the new close confirmation dialog. I like it, but during the UI-review clarkbw and others made good points about some potential usability problems.

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